1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to the structure of a non-volatile semiconductor device using buried element isolation region and a method of manufacturing the semiconductor device.
2. Description of the Related Art
FIG. 1 is a plan view showing a part of a conventional non-volatile memory using a floating gate, and FIG. 2 is a sectional view showing the non-volatile memory along a line I--I in FIG. 1. A non-volatile memory using a floating gate 6 as an electrode wiring layer employs the following method in order to improve a write characteristic. That is, a region 22a doped with a high-concentration impurity of the same conductivity type as that of a semiconductor substrate 1 is formed at a part of a channel region 22 of a transistor to improve a hot carrier effect. In this example, the impurity region 22a having an impurity concentration higher than that of the P-type semiconductor substrate 1 is of a p.sup.- -type. In the above method, the impurity concentration of the channel region 22 cannot be increased throughout the entire region because the characteristics of the transistor are degraded. For this reason, using a photoresist 21 as a mask for the region 22, the high-concentration impurity region 22a is locally formed by implanting ions from an opening 21a. Reference numeral 4 denotes a source diffusion region; 5, a drain diffusion region; 7, a control gate; 10 and 11, gate oxide films; and 20, an element isolation oxide film. According to the prior art using a photoresist, since an alignment margin must be assured for mask alignment precision and thus an occupied area of a cell is increased, formation of a micropatterned non-volatile memory has limitations.